Many integrated circuits (ICs) include a control input for receiving an enabling signal, which is used for activating or deactivating the IC. Such ICs are useful in situations in which ICs are connected and operated in parallel. An example is a plurality of ICs connected to a common communication bus. Another example, where the disabling of individual ICs connected in parallel is important, are chips that are being tested in parallel after manufacturing. Yet another example are ICs that provide functionality, which should only be available in a special test mode, but remain disabled in a normal operation mode.
For example, many chips provide a chip enable (CE) pin, which will activate the IC once a voltage of a predefined level, e.g., 5 V, is supplied to the CE pin. Otherwise the IC is not active or deselected, e.g., if the CE pin is connected to electrical ground.
Such an arrangement is suited for a situation where several chips are connected to a common bus and one chip is selected by a bus arbitrator. The bus arbitrator can be implemented, for example, as a bus controller or a processor controlling the bus. However, such an arrangement requires one control line connected to the CE pin of each integrated circuit on the bus. For example, many memory modules can be connected in parallel, i.e., use the same data and address lines. In order to address the individual modules of a memory bank individually, a control chip decodes the address values and activates only one of the memory modules at a time using a control signal sent to the corresponding memory module. In situations where many integrated circuits are connected and operated in parallel this results in a complicated and thus costly design.
In the second example of chip testing, this is particularly disadvantageous. There, many chips execute test sequences in parallel, controlled by a controller of the testing arrangement. During testing, all chips, which are also called “devices under testing” (DUT), are active and execute the same test sequence. For cost reasons as many chips as possible should be tested at the same time.
However, once a DUT has been identified as being defective, it needs to be excluded from further testing for two reasons. Firstly, to avoid a corruption of further test results through the defective device and, secondly, to preserve the defective device in the erroneous state for further analysis. Thus, the device needs to be deactivated.
If the control lines, e.g., the line connected to the CE pin, of all DUTs were connected in parallel, such an individual deselection would not be possible at all. As a consequence, the defective device would need to be physically removed from the testing arrangement, which is infeasible for a variety of reasons. Firstly, the DUTs are mounted in large testing arrangements, which are contained in a climatic chamber preventing direct access. Secondly, tests are executed continuously in a test run and interrupting the test run would invalidate the results obtained from the non-defective devices as well. Lastly, such a manual interference would be too tedious and costly in a manufacturing environment. Consequently a defective DUT cannot be excluded from further tests and kept in its erroneous state. This is particularly disadvantageous in the testing of non-volatile memory modules. In addition, having to keep a device known to be defective in a testing arrangement can also affect subsequent tests adversely.
In an improved testing arrangement, the controller of the testing arrangement allows the selection or deselection of every DUT. However, this requires a separate line between the controller and each control input of each DUT used in the test. Usually the controller of the testing arrangement will provide only a limited number of control outputs. For example, there are controllers that provide up to a few hundred control outputs. However, many DUTs require a multitude of control signals to be provided, e.g., a chip might comprise 16 control input pins. As a consequence such testing arrangements are limited to a few chips to be tested in parallel, e.g., one per 16 control outputs of the controller of the testing arrangement for chips with 16 control inputs.
In a further refinement of the testing arrangement the DUTs are arranged in an array and a combination of two or more signals are used to activate a particular DUT. Consequently, the control outputs available to a controller of the testing arrangement can be used more efficiently. For example, a controller with 390 control outputs is used to provide an array of 16 rows and 15 columns, totaling 240 DUTs. Each DUT is provided with a multitude of control input signals, i.e., 15 control signals per row of the testing arrangement and 2 signals per column of the testing arrangement.
In another exemplary arrangement, all the CE pins of a column of DUTs are connected together to one control output of the controller. In addition, all command latch enable (CLE) pins common to a row of DUTs are connected to another control output of the controller. Because a chip will only react to a command provided to it if both the CLE and CE pins are connected to a predefined voltage, a single DUT can be enabled by selecting the control output of the controller connected to the line supplying the CE and CLE pins corresponding to the column and the row of the DUT in question. At the same time it is possible to enable all DUTs by selecting all columns and rows at the same time.
These two options are used in combination, for example, during the testing of memory chips. In a first phase all DUTs are enabled and a command is issued to all of them to write a particular test pattern into the memory of the DUTs. In a second phase each DUT is enabled individually and the written pattern is read in and verified. Alternatively, the DUT can comprise a status register, which can be read out by the test controller and provides a status value for the last operation, i.e., whether the operation was completed successfully or failed with an error. Because the reading process is performed much faster than the writing process, the individual selection during the reading process does not slow down the test significantly.
However, if one DUT is known to be defective, it cannot be excluded from further write operations in this arrangement. At best a complete row or column can be deselected by disabling the corresponding control output of the testbed controller. In this case all other devices in the same row or column are excluded from further tests as well, which is equally disadvantageous.